Hardware · Chips

MTIA

MTIA, short for Meta Training and Inference Accelerator, is Meta's own line of AI chips. Training is teaching a model, and inference is running it to answer requests. There are four parts: the 300, 400, 450, and 500. The purchase, including Broadcom's gigawatts, is on the Meta stack.

MTIA 300

On 11 March 2026 the MTIA 300 was in production for ranking and recommendations training. Ranking and recommendation models decide which posts and ads to show people. The 300 is the first MTIA optimized for training those models. It is built from one compute chiplet and two network chiplets, where a chiplet is a small piece of silicon joined with others in one package. Each processing element, one of the chip's small compute blocks, has two RISC-V vector cores. RISC-V is an open standard for a chip's instruction set. A vector core works on many numbers at once. From the MTIA 300 to the MTIA 500, HBM bandwidth increases by 4.5 times and compute FLOPS increases by 25 times, measured from the 300's MX8 format to the 500's MX4. HBM, or high-bandwidth memory, is the fast memory stacked next to the chip. FLOPS counts math operations per second. MX8 and MX4 are number formats that store each value in 8 and 4 bits.

Figure	Value
HBM3E	216 GB
I/O	1.2 TB/s
RDMA NICs (network cards)	Six custom 800 Gbps on each network chiplet
Scale-up	Rack of 16 nodes, up to 1 TB/s
Scale-out	200 GB/s across racks
Processing elements	12 by 6
Message engines	16
Near-memory reduction	More than 2.8 TBs of reduction throughput
GEMMs with collectives	Less than 0.5% compute degradation
HCCL, one rack	Up to 940 GB/s
Recommendation model	150 billion parameters across 40 accelerators
Communication vs a GPU cluster	3.9 times faster

The I/O, HBM3E, and rack figures come from Engineering at Meta, 24 August 2026. The production status comes from Meta's news post of 11 March 2026, which also says hundreds of thousands of MTIA chips are already deployed for inference across organic content and ads. Organic content means regular posts rather than ads. I/O is how fast data moves in and out of the chip. RDMA NICs are network cards that let chips read each other's memory directly. Scale-up links chips inside a rack, and scale-out links racks to each other. GEMMs are the large matrix multiplications at the heart of AI math, and collectives are the group data transfers between chips.

MTIA 400

The 300 evolved into the 400 to support GenAI models while keeping the ranking and recommendation workloads. GenAI, or generative AI, means models that write text or make images. Lab testing of the 400 is finished. On 11 March 2026 Meta said the 400, 450, and 500 will handle all workloads, and will be used mainly for GenAI inference in production in the near future and into 2027.

Figure	Value
Compute chiplets	2
Scale-up domain (chips linked as one group)	72 accelerators
Rack	72 MTIA 400 devices on a switched backplane
FP8 FLOPS vs MTIA 300	400% higher
HBM bandwidth vs MTIA 300	51% higher

MTIA 450

The 400 turned into the 450, tuned for GenAI inference. Meta's 11 March 2026 news post says the 450 and 500 are optimized first for GenAI inference. Mass deployment of the 450 is scheduled for early 2027.

Figure	Value
HBM bandwidth vs MTIA 400	Doubled
MX4 FLOPS vs the prior version	75% higher
MX4 FLOPS vs FP16/BF16	6x
Mass deployment	Early 2027

MTIA 500

The 450 advanced into the 500 for GenAI inference. Mass deployment is scheduled for 2027. The 500 arranges smaller compute chiplets in a 2 by 2 configuration, plus two network chiplets.

Figure	Value
HBM bandwidth vs MTIA 450	50% higher
HBM capacity vs MTIA 450	Up to 80% higher
MX4 FLOPS vs MTIA 450	43% higher
HBM bandwidth, 300 to 500	4.5x
Compute FLOPS, 300 MX8 to 500 MX4	25x
Mass deployment	2027

2nm accelerator

Broadcom's 14 April 2026 release calls the part the industry's first 2nm AI compute accelerator and says the technology supports MTIA. 2nm names the chip manufacturing process, and a smaller number means a newer, denser process. The gigawatt commitment and the 2029 term are on the Meta stack.